The computer and communications industries are rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving computer system manufacturers and communications network and system providers to build networks and systems having greater speed and capacity. In trying to achieve these goals, a common approach taken is to use packet communications and switching technologies operating at ever increasing rates. However, many prior systems are unable to receive and process the information (e.g., packets) received at these higher communications rates. Compounding the problem further, many of the previous techniques are not scalable for use in the faster systems, and thus, new systems and methods are required.
For example, in one implementation of a line card of a communications system, a large number of queues are required to support the various types and destinations of traffic as well as to operate at high data rates (e.g., 125 million packets per second). A well-known technique for implementing a queue is to use a linked list data structure. To operate at the high data rates, an implementation might require very fast data storage elements (e.g., register arrays or flops), and given the typical number of queues required, the number of storage elements required may be too large to implement on an application-specific integrated circuit (ASIC). Also, if an internal or external SRAM is used by an ASIC to implement the queues, the memory access rates of known SRAMs are not fast enough to support the rate required to access and manipulate elements of a queue or linked list implemented using conventional techniques. Thus, needed are new systems and methods for implementing queues and/or linked list data structures.